songyu
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- Name (Pinyin):songyu
- Date of Birth:1969-06-16
- E-Mail:
- Teacher College:计算机科学与工程学院
Contact Information
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- Paper Publications
（会EI）Design and realization of FFT implementation unit based on FPGA
Release time:2023-04-14 Hits:
- Affiliation of Author(s):计算机科学与工程学院
- Journal:MINES 2011
- Funded by:自选课题
- Key Words:FFT；FPGA；Butterfly-calculation；Rotation-factor；Verilog HDL Introduction
- Abstract:This paper describes the arithmetic princple and discipline of FFT,analyzes rotation factor and data address of the node.It adopts flexible Verilog HDL to design and realize the data address unit of FFT implementation which is 64-point by radix-2.It uses Altera company's PLD software Quartus II 8.0(32 Bit) to compile and form top-level entity.
- Co-author:林兴业
- First Author:songyu
- Indexed by:Essay collection
- Page Number:2
- Translation or Not:no
- Date of Publication:2011-11-04